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    Dr. Ashok Kumar Suhag Associate Professor
    • School School of Engineering and Technology
    • Department/Programme Electronics and Communication Engineering
    • Position (additional roles) Area-Rep. - ECE
    • Email ashok.suhag@bmu.edu.in

    Dr. Ashok Kumar Suhag earned his doctorate from Gautam Buddha University in the area of Design for the testability (DFT) specifically on the scan architectures and low power test methodologies. He received his M.Tech in Microelectronics and VLSI design from Kurukshetra University, Kurukshetra and B.E. in Electronics Instrumentation and Control Engineering from the University of Rajasthan.

    He has experience of around eleven years in teaching and research. Prior to joining BMU, he was working at Gautam Buddha University, Greater Noida. He was also previously associated with VIT Jaipur, MEC Bikaner and with a research lab of CSIR that is CSIR- Central Electronics Engineering Research Institute (CEERI) Pilani as a Project Assistant where he worked in the area of MEMS particularly on the fabrication of micro-hotplate.

    His research interests are VLSI testing and design for testability, SoC/NoC design and test & self-healing system design. He has published 15 scholarly articles in various international journals and conferences of repute such as the International Journal of electronics, International journal of circuits and architecture Design, International journal of system assurance engineering and management, vacuum, WRTLT, RASDAT, ISED. He has been an active participant and reviewer for international journals and conferences such as the international journal of electronics, RASDAT, IEEE International Conference on Computer Communication and Control. He is also a lifetime member of the International Association of Engineers and Indian Society for Technical Education and IEEE. Apart from the research and work, his interests include playing cricket, badminton, volleyball, listening to music, travelling and exploring the horizons of traditional Indian culture.

    • Digital logic design (With HDL)
    • Computer Organization and Architecture
    • CMOS VLSI Design
    • Design For Testability
    • Basic of Electrical and Electronic Engineering practice
    • Graduation In: B.Tech (Electronics Instrumentation & Control)
    • Graduation From: University of Rajasthan
    • Graduation Year: 2005
    • Post Graduation In: M.Tech (Microelectronics & VLSI design)
    • Post Graduation From: Deptt. Of Electronics, Kurukshetra University, Kurukshetra
    • Post Graduation Year: 2008
    • Doctorate In: PhD in VLSI Testing
    • Doctorate From: Gautam Buddha University, Gr. Noida
    • Doctorate Year: 2013
    From - To (Year)Designation & Organization
    April 2015-currentAssistant Professor - BMU
    May2010 to April 2015Faculty Associate, Gautam Buddha University, Greater NOIDA
    Jan 2010 to April 2010Sr. Lecturer, VIT, Jaipur
    August 2008 to Dec. 2009Sr. Lecturer, MEC Bikaner
    Feb. 2006 to September 2006Project Assistant, CEERI- Pilani (CSIR lab)
    • VLSI testing and design for testability
    • Memory system design
    • Secure Scan and Low Power VLSI design
    • Suhag A.K. “Reduction of Test Data Volume Using DTESFF-Based Partial Enhanced Scan Method”. In: Yadav N., Yadav A., Bansal J., Deep K., Kim J. (eds) Harmony Search and Nature Inspired Optimization Algorithms. Advances in Intelligent Systems and Computing, pp. 521-526, 2019.
    • Satyadev Ahlawat, Darshit Vaghani, Jaynarayan Tudu and Ashok Suhag “A Cost Effective Technique for Diagnosis of Scan Chain Faults” B. K. Kaushik et al. (Eds.): VDAT 2017, CCIS 711, pp. 191–204, 2017.
    • Ashok Kumar Suhag and Rakesh Sharma “Design and Simulation of Nanoscale Double Gate MOSFET using high K Material and Ballistic Transport Method” Material Today: Proceedings, pp. 10412-10416, 2017.
    • Ashok Kumar Suhag, Satdev Ahlawat, Vivek Shrivastava, Rahul Raj Choudhary “Output Gating Performance Overhead Elimination for Scan Test” International Journal of Electronics,(Taylor and Francis Publication), Vol. 102, Issue 7, pp: 1244-1252, 2015.
    • N Kumar, U Singh, A Sihag, and AK Sinha “Dual frequency gyrotron operating at 42/84 GHz for plasma fusion application” Vacuum (Elsevier Publication) Vol. 113, pp: 43-51, 2015.
    • Anuj Kumar, Ashok Kumar Suhag, Amanpal Singh, Satinder K.Sharma, Mukesh Kumar and Dinesh Kumar “Deposition and Characterization of Amorphous Electroless Ni-Co-P Alloy Thin Film for ULSI Application” Material Research Express, pp: 1244-1252, 2014.
    • Ashok Kumar Suhag, Vivek Shrivastava , Nidhi Singh, “Flip-Flop selection for Partial Enhanced Scan Chain using DTESFF for high Transition Delay fault coverage”, International Journal of System Assurance Engineering and Management (Springer Publication), pp: 303-311, September 2013.
    • A. K. Suhag, Satdev Ahlawat, Vivek Shrivastava , Nidhi Singh “Elimination of Output Gating Performance Overhead for Critical Paths in Scan Test”, International Journal of Circuits and Architecture Design (Inderscience Publication), pp: 62 – 73, 2013.
    • Ashok Suhag, Satdev and Jaynarayan Tudu " Low activity scan FF design for power aware test" 4th IEEE International Workshop on Reliability Aware System Design and Test (RASDAT), Pune, India. January 2013.
    • Ashok Kumar Suhag “Power Aware Scan test” National Conference on Emerging Technologies and Research in Communication, Networking and Signal Processing, February, 8 – 9, 2013.
    • Ashok Kumar Suhag, Vivek Shrivastava “Performance Evaluation of Delay Testable Enhanced Scan Flip-flop” International Journal of System Assurance Engineering and Management (Springer Publication), pp: 169–174, 2012.
    • Satdev, Ashok Suhag, Jaynarayan Tudu, and Virendra Singh, `Power aware scan flip-flop design for scan test`, 13th IEEE Workshop on RTL and High Level testing (WRTLT) 2012, Niigata, Japan, Nov 2012.
    • Suhag, A.K.; Shrivastava, V. “Delay Testable Enhanced Scan Flip-Flop: DFT for High Fault Coverage”, In proc. of IEEE International Symposium on Electronic System Design (ISED), pp. 129 – 133, 2011.
    • G. P. Sinsinwar, K.S.Yadav and Ashok Kumar Suhag “Properties of BDD in Realization of Anti-symmetric Function” National conference on Advancements in Communication, Computing & Signal Processing COMMUNE CACCS-2011 April 16-17, 2011. (Best paper Award)
    • V.K.Khanna, Mahanth Prasad, Ashok Suhag, M.K. Sharma, V.K.Diwedi and Chander Shekhar “Study of the crucial process in the fabrication of MEMS Hotplate Structure” Proceedings of ISSS-MEMS 2006, National Conference on Smart Structures and MEMS Systems for Aerospace Applications, RCI, DRDO, Hyderabad, India, pp.1-6, 1-2 December 2006.
    • V.K.Khanna, Mahanth Prasad, Ashok Suhag, Y.K.Jain M.K. Sharma, V.K.Diwedi and Chander Shekhar “MEMS and Semiconductor Technology-Bases Generic Structures for the Fabrication of High-Performance Chemical Sensors”. National Conference on Sensors and Actuators: Emerging Technological Challenges, CGCRI, Kolkata, Dec21-21, 2006, Abstracts, p.11, Invited Lecture 1-06.
    • Best Paper Award in COMMUNE CACCS-2011

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